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9db106 idt ? six output differential buffer for pcie gen 2 9db106 rev k 04/20/1 1 six output differential buffer for pcie gen 2 da t asheet 1 spread com pa tible pll control logic smb da t smbclk clk_int c l k _ i n c pll_bw iref pciex1 pciex4 clkreq4# clkreq1# pciex(0,2,3,5) descriptionoutput features the 9db106 zero-delay buffer supports pcie gen1 and gen2 cloc king requirements . the 9db106 is dr iv en b y a diff erential src output pair from an idt ck410/ck505-compliant main clockgener ator . it atten uates jitter on the input cloc k and has a selectab le pll bandwidth to maximize performance in systems with or withoutspread-spectrum clocking. an smbus interface allows control of the pll bandwidth and bypass options, while 2 clock request (clkreq#) pins make the 9db106 suitable for express card applications. 6 - 0.7v current mode differential output pairs (hcsl) functional block diagram ke y specifications cycle-to-cycle jitter < 50ps output-to-output skew < 50 ps features/benefits clkreq# pin for outputs 1 and 4/ supports express cardapplications pll or bypass mode/pll can dejitter incoming clock selectable pll bandwidth/minimizes jitter peaking indownstream pll's spread spectrum compatible/tracks spreading input clockfor low emi smbus interface/unused outputs can be disabled recommended applications6 output differential buffer for pcie gen 2
idt ? six output differential buffer for pcie gen 2 9db106 rev k 04/20/1 1 9db106 six output differential buffer for pcie gen 2 2 pin configuration po wer gr oups 28-pin ssop & tssop vdd gnd 7, 13, 16, 22 8,21 pci express outputs tbd tbd smbus n/a 27 iref 28 27 analog vdd & gnd for pll core description pin number pll_bw 1 28 vdda clk_int 2 27 gnda clk_inc 3 26 iref vclkreq1# 4 25 vclkr eq4# pciext0 5 24 pciext5 pciexc0 6 23 pciexc5 vdd 7 22 vdd gnd 8 21 gnd pciext1 9 20 pciext4 pciexc1 10 19 pciexc4 pciext2 11 18 pciext3 pciexc2 12 17 pciexc3 vdd 13 16 vdd smbdat 14 15 smbclk 9db106 120k ohm pull down resistors note: pins preceeded by ' v ' have internal
idt ? six output differential buffer for pcie gen 2 9db106 rev k 04/20/1 1 9db106 six output differential buffer for pcie gen 2 3 pin description pin # pin name pin type description 1 pll_bw in 3.3v input for selecting pll band width 0 = low, 1= high 2 clk_int in true input for differential reference clo ck. 3 clk_inc in complementary input for differential refe rence clock. 4 vclkreq1# in output enable for pci express output pair 1. 0 = enabled, 1 =disabled 5 pciext0 out true clock of differential pci_express p air. 6 pciexc0 out complementary clock of differential pci_ express pair. 7 vdd pwr power supply, nominal 3.3v 8 gnd in ground pin. 9 pciext1 out true clock of differential pci_express p air. 10 pciexc1 out complementary clock of differential pci _express pair. 11 pciext2 out true clock of differential pci_express pair. 12 pciexc2 out complementary clock of differential pci _express pair. 13 vdd pwr power supply, nominal 3.3v 14 smbdat i/o data pin of smbus circuitry, 5v tolerant 15 smbclk in clock pin of smbus circuitry, 5v tolerant 16 vdd pwr power supply, nominal 3.3v 17 pciexc3 out complementary clock of differential pci _express pair. 18 pciext3 out true clock of differential pci_express pair. 19 pciexc4 out complementary clock of differential pci _express pair. 20 pciext4 out true clock of differential pci_express pair. 21 gnd pwr ground pin. 22 vdd pwr power supply, nominal 3.3v 23 pciexc5 out complementary clock of differential pci _express pair. 24 pciext5 out true clock of differential pci_express pair. 25 vclkreq4# in output enable for pci express output pair 4. 0 = enabled, 1 =disabled 26 iref out this pin establishes the reference for the differen tial current-mode output pairs. it requires a fixed precision resisto r to ground. 475ohm is the standard value for 100ohm differentia l impedance. other impedances require different values. see data sheet. 27 gnda pwr ground pin for the pll core. 28 vdda pwr 3.3v power for the pll core. note: pins preceeded by ' v ' have internal 120k ohm pull down resistors
idt ? six output differential buffer for pcie gen 2 9db106 rev k 04/20/1 1 9db106 six output differential buffer for pcie gen 2 4 electrical characteristics - absolute maximum ratin gs parameter symbol conditions min typ max units notes 3.3v core supply voltage vdda 4.6 v 1,2 3.3v logic supply voltage vdd 4.6 v 1,2 input low voltage v il gnd-0.5 v 1 input high voltage v ih except for smbus interface v dd +0.5v v 1 input high voltage v ihsmb smbus clock and data pins 5.5v v 1 storage temperature ts -65 150 c 1 junction temperature tj 125 c 1 input esd protection esd prot human body model 2000 v 1 1 guaranteed by design and characterization, not 100% tested in production. 2 operation under these conditions is neither implied nor guaranteed. electrical characteristics - input/supply/common ou tput parameters ta = t com or t ind; supply voltage vdd = 3.3 v +/-5% parameter symbol conditions min typ max units notes t com commmercial range 0 70 c 1 t ind industrial range -40 85 c 1 input high voltage v ih 3.3 v +/-5% 2 v dd + 0.3 v 1,2 input low voltage v il 3.3 v +/-5% v ss - 0.3 0.8 v 1,2 input high current i ih v in = v dd -5 5 ua 1,2 i il1 v in = 0 v; inputs with no pull- up resistors -5 ua 1,2 i il2 v in = 0 v; inputs with pull-up resistors -200 ua 1,2 full active, c l = full load; 130 150 ma 1 all differential pairs tri-stated 30 40 ma 1 input frequency f i v dd = 3.3 v 80 100 105 mhz pin inductance l pin 7 nh 1 c in logic inputs 5 pf 1 c out output pin capacitance 4.5 pf 1 clk stabilization t stab from vdd reaching 3.1v and input clock stable 1.8 ms 1 input spread spectrum modulation frequency triangular modulation 30 33 khz 1 smbus voltage v dd 2.7 5.5 v 1 low-level output voltage v ol @ i pullup 0.4 v 1 current sinking at v ol = 0.4 v i pullup 4 ma 1 sclk/sdata clock/data rise time t ri2c (max vil - 0.15) to (min vih + 0.15) 1000 ns 1 sclk/sdata clock/data fall time t fi2c (min vih + 0.15) to (max vil - 0.15) 300 ns 1 1 guaranteed by design and characterization, not 100% tested in production. 2 except differential input clock ambient operating temperature input capacitance i dd3.3op operating supply current input low current
idt ? six output differential buffer for pcie gen 2 9db106 rev k 04/20/1 1 9db106 six output differential buffer for pcie gen 2 5 electrical characteristics - clock input parameters ta = t com or t ind; supply voltage vdd = 3.3 v +/-5% parameter symbol conditions min typ max units notes input high voltage - dif_in v ihdif differential inputs (single-ended measurement) 600 800 1150 mv 1 input low voltage - dif_in v ildif differential inputs (single-ended measurement) v ss - 300 0 300 mv 1 input common mode voltage - dif_in v com common mode input voltage 300 1000 mv 1 input amplitude - dif_in v swing peak to peak value 300 1450 mv 1 input slew rate - dif_in dv/dt measured differentiall y 0.4 8 v/ns 1,2 input leakage current i in v in = v dd , v in = gnd -5 5 ua 1 input duty cycle d tin measurement from differential wavefrom 45 55 % 1 input jitter - cycle to cycle j difin differential measurement 0 125 ps 1 1 guaranteed by design and characterization, not 100% tested in production. 2 slew rate measured through +/-75mv window centered around differential zero electrical characteristics - pll parameters ta = t com or t ind; supply voltage vdd = 3.3 v +/-5% group parameter description min typ max units notes pll jitter peaking j peak-hibw (pll_bw = 1) 0 1 2.5 db 1,4 pll jitter peaking j peak-lobw (pll_bw = 0) 0 1 2 db 1,4 pll bandwidth pll hibw (pll_bw = 1) 2 2.5 3 mhz 1,5 pll bandwidth pll lobw (pll_bw = 0) 0.4 0.5 1 mhz 1,5 pcie gen 1 phase jitter (1.5 - 22 mhz) 40 108 ps 1,2,3 pcie gen 2 jitter (8-16 mhz, 5-16 mhz) hi-band >1.5mhz (pll_bw=1) 2.7 3.1 ps rms 1,2,3 pcie gen 2 jitter (8-16 mhz, 5-16 mhz) hi-band >1.5mhz (pll_bw=0) 2.2 3.1 ps rms 1,2,3 pcie gen 2 jitter (8-16 mhz, 5-16 mhz) lo-band <1.5mhz 1.3 3 ps rms 1,2,3 notes: 1. guaranteed by design and characterization, not 1 00% tested in production. 2. see http://www.pcisig.com for complete specs 3. device driven by 932s421bglf or equivalent 4. measured as maximum pass band gain. at frequencies w ithin the loop bw, highest point of magnification is called pll jitter peaking. 5. measured at 3 db dow n or half pow er point. jitter, phase t jphasepll
idt ? six output differential buffer for pcie gen 2 9db106 rev k 04/20/1 1 9db106 six output differential buffer for pcie gen 2 6 electrical characteristics - pciex 0.7v current mod e differential outputs ta = t com or t ind ; v dd = 3.3 v +/-5%; c l =2pf, r s =33.2 , r p =49.9 , i ref = 475 parameter symbol conditions min typ max units notes current source output impedance zo 1 v o = v x 3000 < 1 voltage high vhigh 660 850 1,3 voltage low vlow -150 150 1,3 max voltage vovs 1150 1,3 min voltage vuds -300 1,3 crossing voltage (abs) vcross(abs) 250 550 mv 1,3 crossing voltage (var) d-vcross variation of crossin g over all edges 140 mv 1,3 long accuracy ppm see tperiod min-max values 0 ppm 1,2 100.00mhz nominal 9.9970 10.0030 ns 2 100.00mhz spread 9.9970 10.0533 ns 2 absolute min period t absmin 100.00mhz nominal/spread 9.8720 ns 1,2 rise time t r v ol = 0.175v, v oh = 0.525v 175 700 ps 1 fall time t f v oh = 0.525v v ol = 0.175v 175 700 ps 1 rise time variation d-t r 125 ps 1 fall time variation d-t f 125 ps 1 t pd pll mode. 0 150 ps 1 t pdbyp bypass mode 3.7 4.2 ns 1 duty cycle d t3 measurement from differential wavefrom 45 55 % 1 output-to-output skew t sk3 v t = 50% 40 50 ps 1 pll mode, measurement from differential wavefrom 35 50 ps 1 bypass mode as additive jitter 35 50 ps 1 1 guaranteed by design and characterization, not 100% tested in production. 3 i ref = v dd /(3xr r ). for r r = 475 (1%), i ref = 2.32ma. i oh = 6 x i ref and v oh = 0.7v @ z o =50 . 2 the 9db106 does not add a ppm error to the input cl ock. jitter, cycle to cycle t jcyc-cyc average period t period input to output delay statistical measurement on single ended signal using oscilloscope math function. mv measurement on single ended signal using absolute value. mv
idt ? six output differential buffer for pcie gen 2 9db106 rev k 04/20/1 1 9db106 six output differential buffer for pcie gen 2 7 common recommendations for differential routing dime nsion or value unit figure l1 length, route as non-coupled 50ohm trace 0.5 max i nch 1 l2 length, route as non-coupled 50ohm trace 0.2 max i nch 1 l3 length, route as non-coupled 50ohm trace 0.2 max i nch 1 rs 33 ohm 1 rt 49.9 ohm 1 down device differential routing l4 length, route as coupled microstrip 100ohm diffe rential trace 2 min to 16 max inch 1 l4 length, route as coupled stripline 100ohm differ ential trace 1.8 min to 14.4 max inch 1 differential routing to pci express connector l4 length, route as coupled microstrip 100ohm diffe rential trace 0.25 to 14 max inch 2 l4 length, route as coupled stripline 100ohm differ ential trace 0.225 min to 12.6 max inch 2 src reference clock hcsl output buffer l1 l1' rs l2 l2' rs l4' l4 l3 l3' rt rt pci express down device ref_clk input figure 1: down device routing hcsl output buffer l1 l1' rs l2 l2' rs l4' l4 l3 l3' rt rt pci express add-in board ref_clk input figure 2: pci express connector routing
idt ? six output differential buffer for pcie gen 2 9db106 rev k 04/20/1 1 9db106 six output differential buffer for pcie gen 2 8 vdiff vp-p vcm r1 r2 r3 r4 note 0.45v 0.22v 1.08 33 150 100 100 0.58 0.28 0.6 33 78.7 137 100 0.80 0.40 0.6 33 78.7 none 100 ics874003i-02 input compati ble 0.60 0.3 1.2 33 174 140 100 standard lvds r1a = r1b = r1 r2a = r2b = r2 alternative termination for lvds and other common d ifferential signals (figure 3) hcsl output buffer l1 l1' r1b l2 l2' r1a l4' l4 l3 r2a r2b down device ref_clk input figure 3 l3' r3 r4 component value note r5a, r5b 8.2k 5% r6a, r6b 1k 5% cc 0.1 f vcm 0.350 volts cable connected ac coupled application (figure 4) pcie device ref_clk input figure 4 r5a l4' l4 3.3 volts r5b r6a r6b cc cc
idt ? six output differential buffer for pcie gen 2 9db106 rev k 04/20/1 1 9db106 six output differential buffer for pcie gen 2 9 general smbus serial interface information for the 9db106 ho w to write: ? controller (host) sends a star t bit. ? controller (host) sends the write address d4 (h) ? idt clock will acknowledge ? controller (host) sends the begining byte location = n ? idt clock will acknowledge ? controller (host) sends the data byte count = x ? idt clock will acknowledge ? controller (host) star ts sending byte n thr ough byte n + x -1 ) ? idt clock will acknowledge each byte one at a time ? controller (host) sends a stop bit ho w to read: ? controller (host) will send star t bit. ? controller (host) sends the write address d4 (h) ? idt clock will acknowledge ? controller (host) sends the begining bytelocation = n ? idt clock will acknowledge ? controller (host) will send a separ ate star t bit. ? controller (host) sends the read address d5 (h) ? idt clock will acknowledge ? idt clock will send the data byte count = x ? idt clock sends byte n + x -1 ? idt clock sends byte 0 through byte x (if x (h) was written to b yte 8) . ? controller (host) will need to ac kno wledge each b yte ? controllor (host) will send a not ac kno wledge bit ? controller (host) will send a stop bit idt (slave/receiver) t wr ack ack ack ack ack p stop bit x byte index block write operation slave address d4 (h) beginning byte = n write start bit controller (host) byte n + x - 1 data byte count = x beginning byte n t start bit wr write rt repeat start rd read beginning byte n byte n + x - 1 n not acknowledge p stop bit slave address d5 (h) index block read operation slave address d4 (h) beginning byte = n ack ack data byte count = x ack idt (slave/receiver) controller (host) x byte ack ack
idt ? six output differential buffer for pcie gen 2 9db106 rev k 04/20/1 1 9db106 six output differential buffer for pcie gen 2 10 smbustable: device control register, read/write add ress (d4/d5) pin # name control function type 0 1 pwd bit 7 sw_en enables smbus control of bits (1:0) rw pll controlled by smbus registers pll controlled by device pins 1 bit 6 rw x bit 5 rw x bit 4 rw x bit 3 rw x bit 2 rw x bit 1 pll bw #adjust selects pll bandwidth rw low bw high bw 1 bit 0 pll enable bypasses pll for board test rw pll bypassed (fan out mode) pll enabled (zdb mode) 1 smbustable: output enable register pin # name control function type 0 1 pwd bit 7 rw x bit 6 rw x bit 5 pciex5 output control rw disable enable 1 bit 4 rw x bit 3 pciex3 output control rw disable enable 1 bit 2 pciex2 output control rw disable enable 1 bit 1 rw x bit 0 pciex0 output control rw disable enable 1 smbustable: function select register pin # name control function type 0 1 pwd bit 7 rw x bit 6 rw x bit 5 rw x bit 4 rw x bit 3 rw x bit 2 rw x bit 1 rw x bit 0 rw x smbustable: vendor & revision id register pin # name control function type 0 1 pwd bit 7 rid3 r - - 0 bit 6 rid2 r - - 0 bit 5 rid1 r - - 0 bit 4 rid0 r - - 1 bit 3 vid3 r - - 0 bit 2 vid2 r - - 0 bit 1 vid1 r - - 0 bit 0 vid0 r - - 1 - reserved - reserved - reserved - vendor id -- - - -- - - - - -- - - - byte 3 reserved - 18,17 11,12 - 5,6 byte 2 -- reserved - -- byte 1 - - 24,23 - reserved - - reserved - - reserved - reserved - reserved revision id - reserved byte 0 - - reserved - reserved reserved - reserved - - reserved - reserved
idt ? six output differential buffer for pcie gen 2 9db106 rev k 04/20/1 1 9db106 six output differential buffer for pcie gen 2 11 smbustable: device id pin # name control function type 0 1 pwd bit 7 r 0 bit 6 r 0 bit 5 r 0 bit 4 r 0 bit 3 r 0 bit 2 r 1 bit 1 r 1 bit 0 r 0 smbustable: byte count register pin # name control function type 0 1 pwd bit 7 bc7 rw - - 0 bit 6 bc6 rw - - 0 bit 5 bc5 rw - - 0 bit 4 bc4 rw - - 0 bit 3 bc3 rw - - 0 bit 2 bc2 rw - - 1 bit 1 bc1 rw - - 1 bit 0 bc0 rw - - 0 -- - - - - - - byte 5 - writing to this register will configure how many bytes will be read back, default is 06 = 6 bytes. -- - -- - - byte 4 - - -- -- - - device id = 06 hex
idt ? six output differential buffer for pcie gen 2 9db106 rev k 04/20/1 1 9db106 six output differential buffer for pcie gen 2 12 min max min max a -- 2.00 -- .079 a1 0.05 -- .002 -- a2 1.65 1.85 .065 .073 b 0.22 0.38 .009 .015 c 0.09 0.25 .0035 .010 d e 7.40 8.20 .291 .323 e1 5.00 5.60 .197 .220 e l 0.55 0.95 .022 .037 n a 0 8 0 8 variations min max min max 28 9.90 10.50 .390 .413 10-0033 209 mil ssop n see variations see variations d mm. d (inch) symbol see variations see variations 0.65 basic reference doc.: jedec publication 95, mo-150 0.0256 basic common dimensions in millimeters in inches common dimensions
idt ? six output differential buffer for pcie gen 2 9db106 rev k 04/20/1 1 9db106 six output differential buffer for pcie gen 2 13 indexarea 1 2 n d e1 e seating plane a1 a a2 e - c - b c l aaa c min max min max a -- 1.20 -- .047 a1 0.05 0.15 .002 .006 a2 0.80 1.05 .032 .041 b 0.19 0.30 .007 .012 c 0.09 0.20 .0035 .008 d e e1 4.30 4.50 .169 .177 e l 0.45 0.75 .018 .030 n a 0 8 0 8 aaa -- 0.10 -- .004 variations min max min max 28 9.60 9.80 .378 .386 10-0035 4.40 mm. body, 0.65 mm. pitch tssop 6.40 basic 0.252 basic 0.0256 basic common dimensions in millimeters in inches common dimensions (173 mil) (25.6 mil) symbol see variations see variations 0.65 basic reference doc.: jedec publication 95, mo-153 n see variations see variations d mm. d (inch) ordering information part / order number shipping packaging package tempera ture 9db106bflf tubes 28-pin ssop 0 to +70c 9db106bflft tape and reel 28-pin ssop 0 to +70c 9db106bglf tubes 28-pin tssop 0 to +70c 9db106bglft tape and reel 28-pin tssop 0 to +70c 9DB106BFILF tubes 28-pin ssop -40 to +85c 9DB106BFILFt tape and reel 28-pin ssop -40 to +85c 9db106bgilf tubes 28-pin tssop -40 to +85c 9db106bgilft tape and reel 28-pin tssop -40 to +85c "lf" after the package code are the pb-free configu ration and are rohs compliant. "b" is the device revision designator (will not cor relate to the datasheet revision).
9db106 six output differential buffer for pcie gen 2 innovate with idt and accelerate your future networks. cont act: www .idt .com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for t ech support 408-284-6578 pcclockhelp@id t.com corporate headquarters integrated device t echnology , inc. 6024 silver creek v alley road san jose, ca 95138 united s t ates 800 345 7015 +408 284 8200 (out side u.s.) asia pacific and japan idt singapore pte. ltd. 1 kallang sector #07-01/06 kolamayer industrial park singapore 349276 phone: 65-6-744-3356 fax: 65-6-744-1764 europe idt europe limited 321 kingston road leatherhead, surrey kt22 7tu england phone: 44-1372-363339 fax: 44-1372-378851 ? 2010 integrated device t echnology , inc. all right s reserved. product specifications subject to change without notice. idt , ics, and the idt logo are trademarks of integrated device t echnology , inc. accelerated thinking is a service mark of integrated device t echnology , inc. all other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa revision history rev. originator issue date description page # b rdw 9/12/2005 1. changed output to output skew from 30ps to 45ps. 2. changed pll mode jitter from 40ps to 35ps. 3. changed bypass mode additive jitter from 25ps to 35ps. 4. updated lf ordering information. 5, 8-9 c rdw 8/17/2006 corrected typo of smbus read/write address. 7 d rdw 3/12/2007 added smbus read/write table. 6 e rdw 8/6/2007 1. added phase noise parameters, updated input to o utput delay values. 2. pll bw moved to pll parameters table. 3. added terminations tables. 6-8 f 12/14/2007 updated smbus serial interface informati on. 9 g rdw 4/1/2010 updated ordering info for rev b 13 h rdw 9/15/2010 1. updated ds to include i-temp specs and ordering information 2. updated electrical tables to reflect common set of numbers for i-temp and c-temp 3. converted all references of ics to idt 4. corrected placement of ac coupling caps in figur e 4 j rdw 1/27/2011 updated termination figure 4. 8 k rdw 4/20/2011 1. changed pull down indicator from '* *" to " v " to correct pin description of clkreq# p ins.

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